Memory comprises thousands of cells where information can be stored to be used later. In order to use memory effectively, external devices need to be able to identify where information is stored and need to be able to reliably store information at one point in time and retrieve the same information at a later point in time.
But many memory technologies are subject to some write limitations due to deterioration and damage to memory locations over time, whereby a memory cell cannot be reliably written to (or read from) anymore. For example, some memory locations may suffer from fabrication defects and may never be able to store information. In other cases, memory can be worn out or exhausted. For example, after a number of memory writes to a given memory cell, that cell may wear out and no longer be able to reliably store information. For some memory technologies, such as Dynamic Random Access Memory (DRAM), the number of memory writes required to wear out a given cell can be very large, effectively infinite given today's usage models. But in other technologies, such as Flash and Phase Change Memory (PCM), the number of memory writes required to wear out a given cell can be much smaller, easily exceeded given today's usage models.
Currently, when a cell in a memory can no longer be written to reliably, there are limited ways of fixing this problem. The most simple solution would be to replace the memory. But this can be a costly solution when addressing the failure of a single memory cell in a memory containing millions or billions of other memory cells. Or, the external device using the memory may be able to identify unreliable memory and avoid writing to that location. But this solution requires that the external device have additional logic to detect failing memory locations and the ability to direct memory writes from one location in memory to another. Oftentimes this requires a separate memory controller. Some memory has been created that combines both memory and the logic to remap the memory on the same chip. But due to the different manufacturing processes required to make either efficient memory cells or efficient logic, the performance of the transistors in these hybrid chips is inferior to separate memory or logic. In addition, this design incurs significant costs.